Conventionally, basic operations of companies are processed by mainframes of computers. The mainframes are often called general-purpose computers, general-purpose machines or general-purpose large computers. Typically, the mainframes are connected to various IO devices.
Traditionally, the mainframes have specifically designed circuit or dedicated hardware. For example, IO processor 101 included in mainframe 100 has a specifically designed interrupt control circuit 102, as shown in FIG. 9. IO processor 101 controls data transmission and receipt between one or more IO devices through channel device 110. Channel device 110 controls data transfers between mainframe 100 and the IO devices. The IO devices are, for example, storage devices include in Redundant Arrays of Inexpensive Disks or Redundant Arrays of Independent Disks (RAID) configuration. Interrupt control circuit 102 has hardware circuits and receives interrupts required by one or more channel devices 110 and issues necessary commands to channel devices 110.
Recently, there has been a trend to use general-purpose platforms having the general-purpose processors for implementing large-scale systems. As the general-purpose platform, server systems using operating systems such UNIX (a registered trademark), Linux or Windows (a registered trademark) have been introduced. By using the server systems, costs and periods of developments are reduced and an ease of maintenance is improved.
When shifting to the general-purpose platforms, most users demand to maintain their system as before. For example, to emulate mainframe 100 in platform 200, interrupts to mainframe 100 are controlled as before, as shown in FIG. 9. Thus, channel driver 201 is mounted in general-purpose platform 200 to receive the interrupts required by channel device 110.
Japanese Unexamined Patent Application Publication No. H04-363748 discloses that a central processing unit (CPU) uses a bus provided between a main memory and relinquishes the bus on requests for interrupts required by the channel devices. A direct memory access (DMA) controller or an interrupt controller control the requests from multiple channel devices and select the channel device that the CPU allows to interrupt. A priority of the channel device whose request is accepted is updated to the lowest priority and a channel device prioritized next to the channel device is reprioritized the highest priority by a method to control the requests for interrupt priorities from multiple channel devices.
Japanese Unexamined Patent Application Publication No. S54-14133 discloses an IO channel control method in which a CPU having multiple IO channel devices executes input and output operations with a time-sharing method. A CPU determines priorities of the input and output operations executed by the IO channel devices and the multiple subchannels of the multiple IO channel devices with a machine instruction depending on the IO control devices and according to processing speed of the IO control devices. Therefore, the input and output operations are executed in order of optimum priority with a required efficiency depending on a structure of the IO system.
Japanese Unexamined Patent Application Publication No. S61-233837 discloses an interrupt processing method in which a CPU, a main storage unit, and multiple channel devices are connected through a memory bus. Interrupt priorities of the multiple channel devices are determined by using unique addresses assigned to the main storage unit, and interrupt signals are sent to the CPU through interrupt signaling lines provided to each channel device according to the interrupt priorities.